module uart1(
    input clk,
    input in,
    input reset,
	output done
);
	parameter B0 = 4'd0, B1 = 4'd1, B2 = 4'd2, B3 = 4'd3, B4 = 4'd4, B5 = 4'd5, B6 = 4'd6, B7 = 4'd7;
	parameter IDLE = 4'd8, STOP = 4'd10, DONE = 4'd11, ERR = 4'd12;

	reg [3:0] current_state, next_state;

	always @(posedge clk) begin
		if (reset)
			current_state = IDLE;
		else
			current_state <= next_state;
	end

	always @(*) begin
		next_state = current_state;
		case (current_state)
			IDLE: if (in == 1'b0) next_state = B0;
			B0: next_state = B1;
			B1: next_state = B2;
			B2: next_state = B3;
			B3: next_state = B4;
			B4: next_state = B5;
			B5: next_state = B6;
			B6: next_state = B7;
			B7: next_state = STOP;
			STOP: next_state = (in == 1'b1) ? DONE : ERR;
			DONE: next_state = (in == 1'b1) ? IDLE : B0;
			ERR: if (in == 1'b1) next_state = IDLE;
			default: next_state = IDLE;
		endcase
	end

	assign done = current_state == DONE;

endmodule
